1. Field of the Invention
This invention pertains to the field of automatic handling equipment. More particularly, it pertains to a high speed machine for loading, visually inspecting, and classifying surface mount passive components (a type of miniature electronic component) using extreme care and particular accuracy.
2. Description of the Prior Art
As our society matures, the electronic industry continues to burst forth with new and more diversified products and services. More uses are being found for computers and computer components. As these uses expand, there is constant pressure to reduce the size of computers, their components and the circuitry involved. As an example, the age-old capacitor has shrunk from a cigarette-size cylinder with wires extending from the ends thereof to tiny ceramic devices called "MLCC" (Multi-Layer Chip Capacitors) and "SURFACE MOUNT PASSIVE COMPONENTS", smaller than a grain of rice with metal terminations at the ends thereof. At the present time, these "chips" as they are generically known, have been reduced in size to a ceramic device having overall dimensions of 0.040.times.0.020--0.020 inches. Fifty of them could be set side-by-side within an inch. These chips come in a range of sizes as shown in FIG. 1.
In addition to the pressure to make these components smaller, there is similar pressure to process them faster. In processing chips, numerous electronic tests must be conducted on each to classify them according to their electronic properties. Some of these tests are described in detail in U.S. Pat. No. 5,673,799 but can be summarized as a Dissipation Factor test, a Capacitance Test, a Flash Test, and an Insulation Resistance Test. New tests are constantly being established so that the battery of tests to be conducted on these miniature chips continues to grow.
In order to make processing chips more efficiently, it is necessary to eliminate visibly flawed chips from the electronic testing phase so that overall processing time is reduced and electronic testing is conducted only on those chips that can fulfill all the requirements of the circuitry. Examples of such visually observable flaws are delamination of the dielectric body, cracks in the chip's exterior, divots from the corners or along a marginal edge, or flaws in the metal termination such as smears, spillovers, and unacceptable waviness in the termination paste. These flaws are known to cause changes in the desired electric characteristics of the chip such that they may be segregated for use in less demanding environments.
Accordingly, a movement is underway to subject pre-tested chips to visual checks so that damaged chips can be segregated for use in other areas of the industry, where such flaws can be tolerated, thus making the subsequent electrical testing more efficient and thereby increase handling rates and reduce the costs of producing an acceptable high quality chip. To perform the visual test in an efficient manner, it is necessary to process them at high throughput rates and yet be gentle in handling them. Rates approaching 75,000 per hour are being sought. This means that one machine must visually inspect twenty to twenty-one miniature ceramic chips each second. To do so requires a machine that can handle a huge amount of chips in an efficient manner. However, any overt force applied to the chips, such as crowding them in a confined area or dropping them a distance onto a flat surface will produce its own brand of flaws, usually in the form of cracks in the chip.